Microelectronic package and stacked microelectronic assembly and computing system containing same

ABSTRACT

A microelectronic package comprises a die ( 110, 210 ) and a plurality of electrically conductive layers ( 120, 220 ) and electrically insulating layers ( 130, 230 ), including a first electrically insulating layer ( 131, 231 ) closer to the die than any other electrically insulating layer) and second ( 132, 232 ) and third electrically insulating layers ( 233 ). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE 1  for the second electrically insulating layer is greater than CTE 1  for the first. CTE 2  for the third electrically insulating layer is less than CTE 2  for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer ( 140 ) that is an outermost layer of the microelectronic package.

CLAIM OF PRIORITY

This application is a divisional of U.S. patent application Ser. No.13/976,102, now U.S. Pat. No. ______, filed on Jun. 26, 2013, which wasthe National Stage Entry of PCT/US2011/066049, filed on Dec. 20, 2011.

FIELD OF THE INVENTION

The disclosed embodiments of the invention relate generally to packagingfor microelectronic devices, and relate more particularly to warpagereduction in such packages.

BACKGROUND OF THE INVENTION

Microelectronic device packaging typically contains multiple materials,each with its own coefficient of thermal expansion (CTE). Any systemcharacterized by disparate CTEs is at risk for warpage problems, and,because of their aggressive size scaling, microelectronic packages areperhaps especially vulnerable in this area. Various techniques arecurrently used to overcome or at least mitigate warpage problems inmicroelectronics packaging. While many of these have been at leastsomewhat successful, new approaches are needed in order to more fullyaddress warpage issues.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed embodiments will be better understood from a reading ofthe following detailed description, taken in conjunction with theaccompanying figures in the drawings in which:

FIG. 1 is a cross-sectional view of a microelectronic package accordingto an embodiment of the invention;

FIG. 2 is a cross-sectional view of a microelectronic package accordingto another embodiment of the invention;

FIG. 3 is a cross-sectional view of a stacked microelectronic assemblyaccording to an embodiment of the invention; and

FIG. 4 is a cross-sectional view of a computing system according to anembodiment of the invention.

For simplicity and clarity of illustration, the drawing figuresillustrate the general manner of construction, and descriptions anddetails of well-known features and techniques may be omitted to avoidunnecessarily obscuring the discussion of the described embodiments ofthe invention. Additionally, elements in the drawing figures are notnecessarily drawn to scale. For example, the dimensions of some of theelements in the figures may be exaggerated relative to other elements tohelp improve understanding of embodiments of the present invention.Certain figures may be shown in an idealized fashion in order to aidunderstanding, such as when structures are shown having straight lines,sharp angles, and/or parallel planes or the like that under real-worldconditions would likely be significantly less symmetric and orderly. Thesame reference numerals in different figures denote the same elements,while similar reference numerals may, but do not necessarily, denotesimilar elements.

The terms “first,” “second,” “third,” “fourth,” and the like in thedescription and in the claims, if any, are used for distinguishingbetween similar elements and not necessarily for describing a particularsequential or chronological order. It is to be understood that the termsso used are interchangeable under appropriate circumstances such thatthe embodiments of the invention described herein are, for example,capable of operation in sequences other than those illustrated orotherwise described herein. Similarly, if a method is described hereinas comprising a series of steps, the order of such steps as presentedherein is not necessarily the only order in which such steps may beperformed, and certain of the stated steps may possibly be omittedand/or certain other steps not described herein may possibly be added tothe method. Furthermore, the terms “comprise,” “include,” “have,” andany variations thereof, are intended to cover a non-exclusive inclusion,such that a process, method, article, or apparatus that comprises a listof elements is not necessarily limited to those elements, but mayinclude other elements not expressly listed or inherent to such process,method, article, or apparatus.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,”“under,” and the like in the description and in the claims, if any, areused for descriptive purposes and not necessarily for describingpermanent relative positions unless otherwise indicated eitherspecifically or by context. It is to be understood that the terms soused are interchangeable under appropriate circumstances such that theembodiments of the invention described herein are, for example, capableof operation in other orientations than those illustrated or otherwisedescribed herein. The term “coupled,” as used herein, is defined asdirectly or indirectly connected in an electrical or non-electricalmanner. Objects described herein as being “adjacent to” each other maybe in physical contact with each other, in close proximity to eachother, or in the same general region or area as each other, asappropriate for the context in which the phrase is used. Occurrences ofthe phrase “in one embodiment” herein do not necessarily all refer tothe same embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

Strong demand for small form factor products (phones, tablets, netbooks,notebooks, etc.) has spurred the development of thin-core packages andof coreless packages such as coreless bumpless build-up layer (BBUL-C)packaging. These thin packages are at significant risk for warpage andtherefore need to be strengthened—both at room (operational) temperature(about 25° C.) and, during manufacturing, at elevated (reflow)temperatures (about 260° C.)—in order to mitigate that risk. Embodimentsof the invention make use of different optimized materials to reducewarpage at room and elevated temperatures while maintaining or improvingupon currently-achievable package thickness values.

Referring now to the drawings, FIG. 1 is a cross-sectional view of amicroelectronic package 100 according to an embodiment of the invention.As illustrated in FIG. 1, microelectronic package 100 comprises amicroelectronic die 110, a plurality of electrically conductive layers120 adjacent to the die, and a plurality of electrically insulatinglayers 130 adjacent to the die and arranged in roughly alternatingrelationship with the electrically conductive layers, as shown. Incertain embodiments these electrically conductive and electricallyinsulating layers can be build-up layers that are part of a BBUL or aBBUL-C package. Only a few such layers are illustrated, but it should beunderstood that embodiments may include additional layers similar tothose that are shown in the figure (as suggested by the “Nx”designation, which means that the indicated layers—or similar layers—maybe repeated N times in a particular microelectronic package). Theelectrically insulating layers may comprise dielectric layers, and theelectrically conductive layers may take the form of electricallyconductive traces formed adjacent to each dielectric layer, withconductive vias 127 extending through each dielectric layer to connectthe conductive traces on different layers. Microelectronic package 100further comprises solder balls 180 for connecting the package to amotherboard (not shown) or other next-level component.

Microelectronic die 110 may comprise any type of integrated circuitdevice. In one embodiment, die 110 includes a processing system (eithersingle core or multi-core). For example, the die may comprise amicroprocessor, a graphics processor, a signal processor, a networkprocessor, a chipset, etc. In one embodiment, die 110 comprises asystem-on-chip (SoC) having multiple functional units (e.g., one or moreprocessing units, one or more graphics units, one or more communicationsunits, one or more signal processing units, one or more security units,etc.). However, it should be understood that the disclosed embodimentsare not limited to any particular type or class of IC devices.

Die 110 includes a front-side 112 and an opposing back-side 114. In someembodiments, front-side 112 may be referred to as the “active surface”of the die. An electrical connection between die 110 and the underlyingsubstrate is made using die bumps 115 and plated via interconnects 116(Via0) that connect the die bumps to a first one of electricallyconductive layers 120. Die bumps 115 and via interconnects 116 maycomprise any type of structure and materials (e.g., copper) capable ofproviding electrical communication between die 110 and the substrate,and, according to the illustrated embodiment, the dielectric and metalbuild-up layers that form the substrate may be built up directly overdie 110, in which case a dielectric and subsequent metal layer may beformed directly on front-side 112 of die 110, with the metal layerforming electrical contact with one or more bond pads on the die. Insuch an embodiment, discrete interconnects may not be necessary, asmetallization in the substrate may directly contact a die bond pad.Examples of processes that may utilize the aforementioned techniqueinclude BBUL, die-embedding, and wafer-level packaging.

In other (non-illustrated) embodiments, alternative structures and/ormethods may be utilized to couple die 110 with the substrate. Forexample, die 110 may be disposed on the substrate in a flip-chiparrangement in which interconnects comprise an electrically conductiveterminal on the die (e.g., a pad, bump, stud bump, column, pillar, orother suitable structure or combination of structures) and acorresponding electrically conductive terminal on the substrate (e.g., apad, bump, stud bump, column, pillar, or other suitable structure orcombination of structures). Solder (e.g., in the form of balls or bumps)may be disposed on the terminals of the substrate and/or die, and theseterminals may then be joined using a solder reflow process. Of course,it should be understood that, in other embodiments, many other types ofinterconnects and materials are possible (e.g., wirebonds extendingbetween the die 110 and the substrate). The terminals on die 110 maycomprise any suitable material or any suitable combination of materials,whether disposed in multiple layers or combined to form one or morealloys and/or one or more intermetallic compounds. For example, theterminals on die 110 may include copper, aluminum, gold, silver, nickel,titanium, tungsten, as well as any combination of these and/or othermetals. In other embodiments, a terminal may comprise one or morenon-metallic materials (e.g., a conductive polymer). The terminals onthe substrate may also comprise any suitable material or any suitablecombination of materials, whether disposed in multiple layers orcombined to form one or more alloys and/or one or more intermetalliccompounds. For example, the terminals on the substrate may includecopper, aluminum, gold, silver, nickel, titanium, tungsten, as well asany combination of these and/or other metals. Any suitable soldermaterial may be used to join the mating terminals of the die 110 and thesubstrate, respectively. For example, the solder material may compriseany one or more of tin, copper, silver, gold, lead, nickel, indium, aswell as any combination of these and/or other metals. The solder mayalso include one or more additives and/or filler materials to alter acharacteristic of the solder (e.g., to alter the reflow temperature).

One of electrically insulating layers 130 is an electrically insulatinglayer 131 that is closer to die 110 than any other electricallyinsulating layer in microelectronic package 100. Another one of theelectrically insulating layers is an electrically insulating layer 132,to be further discussed below. Microelectronic package 100 furthercomprises a glass cloth layer 140—also an electrically insulatinglayer—that, as shown, constitutes an outermost layer of themicroelectronic package. Also shown in FIG. 1 is a die backside film(DBF) 150, a package-on-package (PoP) pad and via 160, and anelectrically insulating region 170 that, at least in some embodiments,is formed from—and may be an extension of—electrically insulating layer131. In some embodiments electrically insulating region 170 may containan encapsulation material that may be a silica-filled epoxy, such asbuild-up films available from Ajinomoto Fine-Techno Co., Inc.(hereinafter “Ajinomoto), 1-2 Suzuki-cho, Kawasaki-ku, Kawasaki-shi,210-0801, Japan (e.g. Ajinomoto ABF-GX13, Ajinomoto GX92, and the like).Note that FIG. 1 shows only a portion of microelectronic package 100;additional structure constituting essentially a mirror image of what isshown would typically be located on a side of die 110 opposite the sidewhere PoP pad and via 160 are shown.

A glass cloth layer such as layer 140 is made up of glass fibersencapsulated in a dielectric material. Glass cloth is available—from avariety of vendors (including Ajinomoto)—in various thicknesses andcompositions.

In many existing package configurations, one of electrically insulatinglayers 130 comprises glass cloth and the outermost package layer isoccupied by solder resist. (Subsequent references herein to “existingpackage configurations” or “existing packages” or the like arereferences to a package fitting that description.) Placing the glasscloth in the outermost package layer instead (and in the processdisplacing and eliminating the solder resist), as in FIG. 1, results ina greater thermal moment that reduces package warpage. Because of theglass cloth layer's high modulus and low CTE at temperatures above itsglass transition temperature, the glass cloth is especially effective incombating reflow temperature warpage.

Electrically conductive layers 120 and electrically insulating layers130 are components of a substrate for microelectronic package 100. Thissubstrate—sometimes referred to as a “package substrate”—may compriseany suitable type of substrate capable of providing electricalcommunications between die 110 and a next-level component to whichmicroelectronic package 100 is coupled (e.g., a circuit board). Inanother embodiment, the package substrate may comprise any suitable typeof substrate capable of providing electrical communication between die110 and an upper package that may be coupled with microelectronicpackage 100, and in a further embodiment the package substrate maycomprise any suitable type of substrate capable of providing electricalcommunication between such an upper package and a next-level componentto which microelectronic package 100 is coupled. The package substratemay also provide structural support for die 110. By way of example, inone embodiment, the package substrate comprises a multi-layersubstrate—including alternating layers of a dielectric material andmetal—built up around a core layer (either a dielectric or metal core).In another embodiment, the substrate comprises a coreless multi-layersubstrate. Other types of substrates and substrate materials may alsofind use with the disclosed embodiments (e.g., ceramics, sapphire,glass, etc.). In the illustrated embodiment, as has been mentioned, thesubstrate may comprise alternating layers of dielectric material andmetal that are built-up over the die itself; this process is sometimesreferred to as a “bumpless build-up process.” Where such an approach isutilized, solder interconnects may not be needed and may be replaced bydirectly-plated copper via interconnects, as the build-up layers may bedisposed directly over die 110.

Electrically insulating layer 132 is farther from die 110 than any otherelectrically insulating layer besides glass cloth layer 140. In oneembodiment, electrically insulating layer 132 comprises a glass clothlayer having a thickness no greater than 75 micrometers (also referredto herein using the designations “microns” and “μm”). In anotherembodiment, electrically insulating layer 132 again comprises a glasscloth layer, this time having a thickness no greater than 55 microns.(In these embodiments, a solder resist layer may be substituted forglass cloth layer 140.) Modeling results indicate that a 55-μm glasscloth layer is more effective in reducing warpage than is a 75-μm glasscloth layer—likely due to the higher volume fraction of glass fiberscompared to the surrounding dielectric material in the sheath used tocontain the glass fibers. Increasingly smaller thicknesses are likely tobe increasingly effective in this regard.

In yet another embodiment, electrically insulating layer 132 comprises adielectric material (not necessarily a glass cloth layer) having athickness no greater than 30 microns. This embodiment yields bothwarpage reduction benefits and overall package thickness benefits.Warpage is reduced, as explained above, due to the presence in thepackage of glass cloth layer 140—that is, of a glass cloth layer as thepackage's outermost layer. Overall package thickness is less than thatof existing package configurations due to the presence in the inventiveembodiment of a thin (e.g., 30 μm) dielectric layer at a particularinterior package location as opposed to the presence of a glass cloth atthat location in the existing package.

It was mentioned above that embodiments of the invention feature a glasscloth layer (rather than the existing package's solder resist material)in the outermost package layer instead of in its more typical positionas one of the package's interior electrically insulating layers (such aslayers 130 in FIG. 1). Not stated in that earlier discussion is the factmentioned immediately above, namely, that those inventive embodimentsmay have electrically insulating layers that are thinner than those ofan existing package, thus providing an overall package thicknessbenefit. Also contributing to the thickness benefit is the fact that theoutermost layer does not figure in the overall package thicknesscalculation, as the solder ball is attached to the last conduction layerwhich lies above the outermost layer.

FIG. 2 is a cross-sectional view of a microelectronic package 200according to an embodiment of the invention. In many respectsmicroelectronic package 200 is similar to microelectronic package 100 ofFIG. 1, but there are certain distinctions between the two packages, asdiscussed below.

As illustrated in FIG. 2, microelectronic package 200 comprises amicroelectronic die 210 (with a front side 212 and a backside 214), aplurality of electrically conductive layers 220 adjacent to the die, anda plurality of electrically insulating layers 230 adjacent to the dieand arranged in roughly alternating relationship with the electricallyconductive layers, as shown. Die bumps 215 and plated vias 216 extendfrom the die's front side 212 and electrically connect die 210 with theunderlying substrate. Conductive vias 227 extend through eachelectrically insulating layer to connect the conductive traces ondifferent layers. In certain embodiments these electrically conductiveand electrically insulating layers can be build-up layers that are partof a BBUL or a BBUL-C package. Only a few such layers are illustrated,but it should be understood that embodiments may include additionallayers similar to those that are shown in the figure (as suggested bythe “Nx” designation, which means that the indicated layers—or similarlayers—may be repeated N times in a particular microelectronic package).

One of electrically insulating layers 230 is an electrically insulatinglayer 231 that is closer to die 210 than any other electricallyinsulating layer in microelectronic package 200. Additional electricallyinsulating layers will be introduced and discussed below.Microelectronic package 200 further comprises a DBF 250, a PoP pad andvia 260, an electrically insulating region 270 that, at least in someembodiments, is formed from—and may be an extension of—electricallyinsulating layer 231, and solder balls 280. Note that FIG. 2 shows onlya portion of microelectronic package 200; additional structureconstituting essentially a mirror image of what is shown would typicallybe located on a side of die 210 opposite the side where PoP pad and via260 are shown.

Microelectronic package 200 further comprises electrically insulatinglayers 232 and 233. In the illustrated embodiment, electricallyinsulating layer 233 constitutes an outermost layer of microelectronicpackage 200, while electrically insulating layer 232 is farther from die210 than any other electrically insulating layer besides electricallyinsulating layer 233. In other embodiments, at least one of which willbe discussed in detail below, the locations of layers 232 and 233 may bereversed or otherwise altered.

Electrically insulating layer 231 has a first glass transitiontemperature, a first coefficient of thermal expansion, and a firstmodulus of elasticity. Electrically insulating layer 232 has a secondglass transition temperature, a second coefficient of thermal expansion,and a second modulus of elasticity. Electrically insulating layer 233has a third glass transition temperature, a third coefficient of thermalexpansion, and a third modulus of elasticity. Each of these parametersmay, according to embodiments of the invention, be chosen so as to havea beneficial effect on warpage reduction for microelectronic package200, as detailed below.

In one embodiment, the second modulus of elasticity is greater than thefirst modulus of elasticity. This means that electrically insulatinglayer 232 is stiffer and more rigid than electrically insulating layer231. By placing such a layer as far or nearly as far as possible fromthe die the shear-stress induced thermal moment can be increased,leading to warpage reduction.

In the same or another embodiment, the second coefficient of thermalexpansion at a temperature less than the second glass transitiontemperature—i.e., at temperatures equal to or close to roomtemperature—is lower than the first coefficient of thermal expansion ata temperature lower than the first glass transition temperature. It willbe convenient to use hereinafter the notation “CTE₁” to refer to the CTEof a material at a temperature below the material's glass transitiontemperature and the notation “CTE₂” to refer to the CTE of a material ata temperature above the material's glass transition temperature. Usingthis notation, the previous concept may be stated as follows: CTE₁ ofelectrically insulating layer 232 is lower than CTE₁ of electricallyinsulating layer 231. Furthermore, CTE₂ of electrically insulating layer233 is less than CTE₂ of electrically insulating layer 231.

In an embodiment like that illustrated in FIG. 2, where electricallyinsulating layer 233 constitutes an outermost layer of microelectronicpackage 200 and electrically insulating layer 232 is farther from die210 than all other insulating layers except for electrically insulatinglayer 233, both electrically insulating layer 232 and electricallyinsulating layer 233 can comprise a glass cloth material. In a different(non-illustrated) embodiment where electrically insulating layer 232constitutes an outermost layer of the microelectronic package andelectrically insulating layer 233 is farther from the die than any otherelectrically insulating layer other than electrically insulating layer232—electrically insulating layer 232 can comprise one of a glass cloth,including a particular glass cloth type that is formed from acyanate-based resin, a mold compound, and a filled epoxy (e.g., ahighly-filled epoxy such as epoxy filled with 90% silica), andelectrically insulating layer 233 can comprise a glass cloth.

A glass cloth used as the outermost layer (or near outermost layer) isvery effective in reducing warpage of a coreless package both at roomand elevated (e.g., reflow) temperatures because of its high modulus andlow CTE₁ & CTE₂. Additionally, the room temperature warpage can bereduced still further—even significantly reduced—by the use of avery-high modulus (higher than glass cloth), low CTE₁ (lower than glasscloth) material in one of the outermost package layers. In other words,by using two different optimized materials in specific locations, it ispossible, according to embodiments of the invention, to effectivelylower package warpage at both room and reflow temperatures.

Referring again briefly to FIG. 1, in light of the newly-introducedCTE/glass transition temperature notation, it may now be mentioned thatlayers 132 and 140 could be swapped; i.e., the layer 132 material may bechosen so as to have ideal CTE₂ for reflow temperature warpage reductionand the layer 140 material may be chosen so as to have ideal CTE₁ forroom temperature reduction.

FIG. 3 is a cross-sectional view of a stacked microelectronic assembly300 according to an embodiment of the invention. As illustrated in FIG.3, stacked microelectronic assembly 300 comprises microelectronicpackage 200 (with features, components, and details as described above)and a microelectronic package 301 over microelectronic package 200. Inone embodiment, then, stacked microelectronic assembly 300 is a PoPassembly. According to one embodiment, microelectronic package 301includes one or more memory devices. In another embodiment,microelectronic package 301 comprises a wireless communications system(or, alternatively, includes one or more components of a communicationssystem). In a further embodiment, microelectronic package 301 includes agraphics processing system. Stacked microelectronic assembly 300 maycomprise part of any type of computing system, such as a hand-heldcomputing system (e.g., a cell phone, smart phone, music player, etc.),mobile computing system (e.g., a laptop, nettop, tablet, etc.), adesktop computing system, or a server. In one embodiment, stackedmicroelectronic assembly 300 comprises a solid state drive (SSD).

Microelectronic package 301 may comprise any suitable package structure.In one embodiment, microelectronic package 301 comprises an integratedcircuit (IC) die 310 (such as a memory die) disposed on a substrate 305,and electrically (and perhaps mechanically) coupled with the substrateby interconnects that can take one of the forms described below. In theillustrated embodiment, IC die 310 is disposed on substrate 305 in aflip-chip arrangement with solder bumps 315, and each of theinterconnects may comprise an electrically conductive terminal on die310 (e.g., a conductive pad, conductive bump, conductive pillar, orother structure or combination of structures) and a mating conductiveterminal on substrate 305 (e.g., a conductive pad, conductive bump,conductive pillar, or other structure or combination of structures) thatare electrically coupled by, for example, a solder reflow process. Inanother embodiment, IC die 310 may be electrically coupled withsubstrate 305 by one or more wirebonds (not shown), and a layer of dieattach adhesive (also not shown) disposed between the die and thesubstrate may aid in mechanically securing the die to the substrate. Ina further embodiment, two or more IC dies—one of which may be IC die310—may be disposed above substrate 305, and each IC die may beelectrically coupled with the substrate by the aforementioned flip-chipinterconnects or by wirebonds, or by any suitable combination of theseinterconnect structures or other types of interconnects. In yet afurther embodiment, one or more of the IC dies may be stacked over oneof the other IC dies.

A plurality of interconnects 325 electrically couple microelectronicpackage 301 with microelectronic package 200. Each of the interconnects325 may comprise any type of structure and material (or materials)capable of providing electrical communication between the upper andlower IC packages. According to one embodiment, an interconnect 325comprises a reflowed solder bump extending between a terminal (e.g., PoPpad 260 or some other pad, bump, column, or pillar) on a surface ofmicroelectronic package 200 and a mating terminal 360 (e.g., a pad,bump, column, or pillar) on a surface of microelectronic package 301. Inone embodiment, the array of interconnects 325 also aid in mechanicallysecuring microelectronic package 301 to microelectronic package 200. Ofcourse, it should be understood that many other types of interconnectsand materials are possible (e.g., wirebonds).

FIG. 4 is a cross-sectional view of a computing system 400 according toan embodiment of the invention. System 400 includes a number ofcomponents disposed on a circuit board, mainboard, or other board 410.Board 410 includes a first side 412 and an opposing second side 414, andvarious components may be disposed on either one or both of the firstand second sides 412, 414. In the illustrated embodiment, the computingsystem 400 includes stacked microelectronic assembly 300 (with features,components, and details as described above) disposed on side 412. System400 may comprise any type of computing system, such as, for example, ahand-held or mobile computing device (e.g., a cell phone, a smart phone,a mobile internet device, a music player, a tablet computer, a laptopcomputer, a nettop computer, etc.). However, the disclosed embodimentsare not limited to hand-held and other mobile computing devices andthese embodiments may find application in other types of computingsystems, such as desk-top computers and servers.

Board 410 may comprise any suitable type of circuit board or othersubstrate capable of providing electrical communication between one ormore of the various components disposed on the board. In one embodiment,for example, board 410 comprises a printed circuit board (PCB)comprising multiple metal layers separated from one another by a layerof dielectric material and interconnected by electrically conductivevias. Any one or more of the metal layers may be formed in a desiredcircuit pattern to route—perhaps in conjunction with other metallayers—electrical signals between the components coupled with board 410.However, it should be understood that the disclosed embodiments are notlimited to the above-described PCB and, further, that board 410 maycomprise any other suitable substrate.

In addition to stacked microelectronic assembly 300, one or moreadditional components may be disposed on either one or both sides 412,414 of board 410. By way of example, as shown in the figures, components401 may be disposed on side 412 of board 410, and components 402 may bedisposed on the board's opposing side 414. Additional components thatmay be disposed on board 410 include other IC devices (e.g., processingdevices, memory devices, signal processing devices, wirelesscommunication devices, graphics controllers and/or drivers, audioprocessors and/or controllers, etc.), power delivery components (e.g., avoltage regulator and/or other power management devices, a power supplysuch as a battery, and/or passive devices such as a capacitor), and oneor more user interface devices (e.g., an audio input device, an audiooutput device, a keypad or other data entry device such as a touchscreen display, and/or a graphics display, etc.), as well as anycombination of these and/or other devices. In one embodiment, computingsystem 400 includes a radiation shield. In a further embodiment,computing system 400 includes a cooling solution. In yet anotherembodiment, computing system 400 includes an antenna. In yet a furtherembodiment, system 400 may be disposed within a housing or case. Whereboard 410 is disposed within a housing, some of the components ofcomputer system 400—e.g., a user interface device, such as a display orkeypad, and/or a power supply, such as a battery—may be electricallycoupled with board 410 (and/or a component disposed on this board) butmay be mechanically coupled with the housing.

Although the invention has been described with reference to specificembodiments, it will be understood by those skilled in the art thatvarious changes may be made without departing from the spirit or scopeof the invention. Accordingly, the disclosure of embodiments of theinvention is intended to be illustrative of the scope of the inventionand is not intended to be limiting. It is intended that the scope of theinvention shall be limited only to the extent required by the appendedclaims. For example, to one of ordinary skill in the art, it will bereadily apparent that the microelectronic package and the relatedstructures and methods discussed herein may be implemented in a varietyof embodiments, and that the foregoing discussion of certain of theseembodiments does not necessarily represent a complete description of allpossible embodiments.

Additionally, benefits, other advantages, and solutions to problems havebeen described with regard to specific embodiments. The benefits,advantages, solutions to problems, and any element or elements that maycause any benefit, advantage, or solution to occur or become morepronounced, however, are not to be construed as critical, required, oressential features or elements of any or all of the claims.

Moreover, embodiments and limitations disclosed herein are not dedicatedto the public under the doctrine of dedication if the embodiments and/orlimitations: (1) are not expressly claimed in the claims; and (2) are orare potentially equivalents of express elements and/or limitations inthe claims under the doctrine of equivalents.

What is claimed is:
 1. A microelectronic package comprising: amicroelectronic die; a plurality of electrically conductive layers; aplurality of electrically insulating layers including: a firstelectrically insulating layer closer to the die than any otherelectrically insulating layer; and a second electrically insulatinglayer; and a first glass cloth layer comprising a plurality of glassfibers encapsulated in a dielectric material, the first glass clothlayer constituting an outermost layer of the microelectronic package. 2.The microelectronic package of claim 1 wherein: the second electricallyinsulating layer is farther from the die than any other electricallyinsulating layer other than the first glass cloth layer.
 3. Themicroelectronic package of claim 2 wherein: the second electricallyinsulating layer comprises a second glass cloth layer having a thicknessno greater than 75 micrometers.
 4. The microelectronic package of claim2 wherein: the second electrically insulating layer comprises a secondglass cloth layer having a thickness no greater than 55 micrometers. 5.The microelectronic package of claim 2 wherein: the second electricallyinsulating layer comprises a dielectric material having a thickness nogreater than 30 micrometers.